first commit
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lethanhsonvsp
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serializedVersion: 2
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defaultReferences: []
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executionOrder: 0
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fileFormatVersion: 2
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guid: a097ced0beed3e04abd3fa933657e0c3
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serializedVersion: 2
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defaultReferences: []
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executionOrder: 0
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using System;
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using System.Diagnostics;
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namespace Unity.Burst.Intrinsics
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{
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public unsafe static partial class Arm
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{
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public unsafe partial class Neon
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{
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/// <summary>
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/// Evaluates to true at compile time if Armv8.1 Crypto intrinsics (AES, SHA1, SHA2, CRC32) are supported.
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/// </summary>
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public static bool IsNeonCryptoSupported { get { return false; } }
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/// <summary>SHA1 hash update (choose).
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/// <br/>Equivalent instruction: <c>SHA1C Qd,Sn,Vm.4S</c></summary>
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/// <param name="a0">128-bit vector a0</param>
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/// <param name="a1">UInt32 a1</param>
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/// <param name="a2">128-bit vector a2</param>
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/// <returns>128-bit vector</returns>
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[DebuggerStepThrough]
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public static v128 vsha1cq_u32(v128 a0, UInt32 a1, v128 a2)
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{
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throw new NotImplementedException();
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}
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/// <summary>SHA1 hash update (parity).
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/// <br/>Equivalent instruction: <c>SHA1P Qd,Sn,Vm.4S</c></summary>
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/// <param name="a0">128-bit vector a0</param>
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/// <param name="a1">UInt32 a1</param>
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/// <param name="a2">128-bit vector a2</param>
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/// <returns>128-bit vector</returns>
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[DebuggerStepThrough]
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public static v128 vsha1pq_u32(v128 a0, UInt32 a1, v128 a2)
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{
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throw new NotImplementedException();
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}
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/// <summary>SHA1 hash update (majority).
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/// <br/>Equivalent instruction: <c>SHA1M Qd,Sn,Vm.4S</c></summary>
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/// <param name="a0">128-bit vector a0</param>
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/// <param name="a1">UInt32 a1</param>
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/// <param name="a2">128-bit vector a2</param>
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/// <returns>128-bit vector</returns>
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[DebuggerStepThrough]
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public static v128 vsha1mq_u32(v128 a0, UInt32 a1, v128 a2)
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{
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throw new NotImplementedException();
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}
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/// <summary>SHA1 fixed rotate.
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/// <br/>Equivalent instruction: <c>SHA1H Sd,Sn</c></summary>
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/// <param name="a0">UInt32 a0</param>
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/// <returns>UInt32</returns>
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[DebuggerStepThrough]
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public static UInt32 vsha1h_u32(UInt32 a0)
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{
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throw new NotImplementedException();
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}
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/// <summary>SHA1 schedule update 0.
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/// <br/>Equivalent instruction: <c>SHA1SU0 Vd.4S,Vn.4S,Vm.4S</c></summary>
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/// <param name="a0">128-bit vector a0</param>
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/// <param name="a1">128-bit vector a1</param>
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/// <param name="a2">128-bit vector a2</param>
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/// <returns>128-bit vector</returns>
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[DebuggerStepThrough]
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public static v128 vsha1su0q_u32(v128 a0, v128 a1, v128 a2)
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{
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throw new NotImplementedException();
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}
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/// <summary>SHA1 schedule update 1.
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/// <br/>Equivalent instruction: <c>SHA1SU1 Vd.4S,Vn.4S</c></summary>
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/// <param name="a0">128-bit vector a0</param>
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/// <param name="a1">128-bit vector a1</param>
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/// <returns>128-bit vector</returns>
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[DebuggerStepThrough]
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public static v128 vsha1su1q_u32(v128 a0, v128 a1)
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{
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throw new NotImplementedException();
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}
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/// <summary>SHA256 hash update (part 1).
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/// <br/>Equivalent instruction: <c>SHA256H Qd,Qn,Vm.4S</c></summary>
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/// <param name="a0">128-bit vector a0</param>
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/// <param name="a1">128-bit vector a1</param>
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/// <param name="a2">128-bit vector a2</param>
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/// <returns>128-bit vector</returns>
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[DebuggerStepThrough]
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public static v128 vsha256hq_u32(v128 a0, v128 a1, v128 a2)
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{
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throw new NotImplementedException();
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}
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/// <summary>SHA256 hash update (part 2).
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/// <br/>Equivalent instruction: <c>SHA256H2 Qd,Qn,Vm.4S</c></summary>
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/// <param name="a0">128-bit vector a0</param>
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/// <param name="a1">128-bit vector a1</param>
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/// <param name="a2">128-bit vector a2</param>
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/// <returns>128-bit vector</returns>
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[DebuggerStepThrough]
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public static v128 vsha256h2q_u32(v128 a0, v128 a1, v128 a2)
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{
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throw new NotImplementedException();
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}
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/// <summary>SHA256 schedule update 0.
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/// <br/>Equivalent instruction: <c>SHA256SU0 Vd.4S,Vn.4S</c></summary>
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/// <param name="a0">128-bit vector a0</param>
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/// <param name="a1">128-bit vector a1</param>
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/// <returns>128-bit vector</returns>
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[DebuggerStepThrough]
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public static v128 vsha256su0q_u32(v128 a0, v128 a1)
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{
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throw new NotImplementedException();
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}
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/// <summary>SHA256 schedule update 1.
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/// <br/>Equivalent instruction: <c>SHA256SU1 Vd.4S,Vn.4S,Vm.4S</c></summary>
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/// <param name="a0">128-bit vector a0</param>
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/// <param name="a1">128-bit vector a1</param>
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/// <param name="a2">128-bit vector a2</param>
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/// <returns>128-bit vector</returns>
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[DebuggerStepThrough]
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public static v128 vsha256su1q_u32(v128 a0, v128 a1, v128 a2)
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{
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throw new NotImplementedException();
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}
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/// <summary>CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
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/// <br/>Equivalent instruction: <c>CRC32B Wd,Wn,Wm</c></summary>
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/// <param name="a0">UInt32 a0</param>
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/// <param name="a1">Byte a1</param>
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/// <returns>UInt32</returns>
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[DebuggerStepThrough]
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public static UInt32 __crc32b(UInt32 a0, Byte a1)
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{
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throw new NotImplementedException();
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}
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||||
/// <summary>CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
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/// <br/>Equivalent instruction: <c>CRC32H Wd,Wn,Wm</c></summary>
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/// <param name="a0">UInt32 a0</param>
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/// <param name="a1">UInt16 a1</param>
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/// <returns>UInt32</returns>
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[DebuggerStepThrough]
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public static UInt32 __crc32h(UInt32 a0, UInt16 a1)
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{
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throw new NotImplementedException();
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}
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||||
/// <summary>CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
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/// <br/>Equivalent instruction: <c>CRC32W Wd,Wn,Wm</c></summary>
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/// <param name="a0">UInt32 a0</param>
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/// <param name="a1">UInt32 a1</param>
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/// <returns>UInt32</returns>
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[DebuggerStepThrough]
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public static UInt32 __crc32w(UInt32 a0, UInt32 a1)
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{
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throw new NotImplementedException();
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||||
}
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||||
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||||
/// <summary>CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
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/// <br/>Equivalent instruction: <c>CRC32X Wd,Wn,Xm</c></summary>
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/// <param name="a0">UInt32 a0</param>
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/// <param name="a1">UInt64 a1</param>
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/// <returns>UInt32</returns>
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[DebuggerStepThrough]
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||||
public static UInt32 __crc32d(UInt32 a0, UInt64 a1)
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{
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throw new NotImplementedException();
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||||
}
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||||
|
||||
/// <summary>CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
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||||
/// <br/>Equivalent instruction: <c>CRC32CB Wd,Wn,Wm</c></summary>
|
||||
/// <param name="a0">UInt32 a0</param>
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||||
/// <param name="a1">Byte a1</param>
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||||
/// <returns>UInt32</returns>
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||||
[DebuggerStepThrough]
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||||
public static UInt32 __crc32cb(UInt32 a0, Byte a1)
|
||||
{
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||||
throw new NotImplementedException();
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||||
}
|
||||
|
||||
/// <summary>CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
|
||||
/// <br/>Equivalent instruction: <c>CRC32CH Wd,Wn,Wm</c></summary>
|
||||
/// <param name="a0">UInt32 a0</param>
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/// <param name="a1">UInt16 a1</param>
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||||
/// <returns>UInt32</returns>
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||||
[DebuggerStepThrough]
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||||
public static UInt32 __crc32ch(UInt32 a0, UInt16 a1)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
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||||
/// <br/>Equivalent instruction: <c>CRC32CW Wd,Wn,Wm</c></summary>
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||||
/// <param name="a0">UInt32 a0</param>
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/// <param name="a1">UInt32 a1</param>
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/// <returns>UInt32</returns>
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||||
[DebuggerStepThrough]
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||||
public static UInt32 __crc32cw(UInt32 a0, UInt32 a1)
|
||||
{
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throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.
|
||||
/// <br/>Equivalent instruction: <c>CRC32CX Wd,Wn,Xm</c></summary>
|
||||
/// <param name="a0">UInt32 a0</param>
|
||||
/// <param name="a1">UInt64 a1</param>
|
||||
/// <returns>UInt32</returns>
|
||||
[DebuggerStepThrough]
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||||
public static UInt32 __crc32cd(UInt32 a0, UInt64 a1)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>AES single round encryption.
|
||||
/// <br/>Equivalent instruction: <c>AESE Vd.16B,Vn.16B</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
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||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
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||||
public static v128 vaeseq_u8(v128 a0, v128 a1)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>AES single round decryption.
|
||||
/// <br/>Equivalent instruction: <c>AESD Vd.16B,Vn.16B</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
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||||
public static v128 vaesdq_u8(v128 a0, v128 a1)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>AES mix columns.
|
||||
/// <br/>Equivalent instruction: <c>AESMC Vd.16B,Vn.16B</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vaesmcq_u8(v128 a0)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>AES inverse mix columns.
|
||||
/// <br/>Equivalent instruction: <c>AESIMC Vd.16B,Vn.16B</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vaesimcq_u8(v128 a0)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
fileFormatVersion: 2
|
||||
guid: db8f2de394d138e1967d236540227a26
|
||||
MonoImporter:
|
||||
serializedVersion: 2
|
||||
defaultReferences: []
|
||||
executionOrder: 0
|
||||
icon: {instanceID: 0}
|
||||
externalObjects: {}
|
||||
userData:
|
||||
assetBundleName:
|
||||
assetBundleVariant:
|
||||
@@ -0,0 +1,168 @@
|
||||
using System;
|
||||
using System.Diagnostics;
|
||||
|
||||
namespace Unity.Burst.Intrinsics
|
||||
{
|
||||
public unsafe static partial class Arm
|
||||
{
|
||||
public unsafe partial class Neon
|
||||
{
|
||||
/// <summary>
|
||||
/// Evaluates to true at compile time if Armv8.2 Dot Product intrinsics are supported.
|
||||
/// </summary>
|
||||
public static bool IsNeonDotProdSupported { get { return false; } }
|
||||
|
||||
/// <summary>Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
|
||||
/// <br/>Equivalent instruction: <c>UDOT Vd.2S,Vn.8B,Vm.8B</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vdot_u32(v64 a0, v64 a1, v64 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
|
||||
/// <br/>Equivalent instruction: <c>SDOT Vd.2S,Vn.8B,Vm.8B</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vdot_s32(v64 a0, v64 a1, v64 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
|
||||
/// <br/>Equivalent instruction: <c>UDOT Vd.4S,Vn.16B,Vm.16B</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vdotq_u32(v128 a0, v128 a1, v128 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
|
||||
/// <br/>Equivalent instruction: <c>SDOT Vd.4S,Vn.16B,Vm.16B</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vdotq_s32(v128 a0, v128 a1, v128 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
|
||||
/// <br/>Equivalent instruction: <c>UDOT Vd.2S,Vn.8B,Vm.4B[lane]</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..1]</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vdot_lane_u32(v64 a0, v64 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
|
||||
/// <br/>Equivalent instruction: <c>SDOT Vd.2S,Vn.8B,Vm.4B[lane]</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..1]</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vdot_lane_s32(v64 a0, v64 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
|
||||
/// <br/>Equivalent instruction: <c>UDOT Vd.4S,Vn.16B,Vm.4B[lane]</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vdotq_laneq_u32(v128 a0, v128 a1, v128 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
|
||||
/// <br/>Equivalent instruction: <c>SDOT Vd.4S,Vn.16B,Vm.4B[lane]</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vdotq_laneq_s32(v128 a0, v128 a1, v128 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
|
||||
/// <br/>Equivalent instruction: <c>UDOT Vd.2S,Vn.8B,Vm.4B[lane]</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vdot_laneq_u32(v64 a0, v64 a1, v128 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
|
||||
/// <br/>Equivalent instruction: <c>SDOT Vd.2S,Vn.8B,Vm.4B[lane]</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vdot_laneq_s32(v64 a0, v64 a1, v128 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Dot Product unsigned arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
|
||||
/// <br/>Equivalent instruction: <c>UDOT Vd.4S,Vn.16B,Vm.4B[lane]</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..1]</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vdotq_lane_u32(v128 a0, v128 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.
|
||||
/// <br/>Equivalent instruction: <c>SDOT Vd.4S,Vn.16B,Vm.4B[lane]</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..1]</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vdotq_lane_s32(v128 a0, v128 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
fileFormatVersion: 2
|
||||
guid: ae2473ecba7e346e806e9120b6533cf4
|
||||
MonoImporter:
|
||||
serializedVersion: 2
|
||||
defaultReferences: []
|
||||
executionOrder: 0
|
||||
icon: {instanceID: 0}
|
||||
externalObjects: {}
|
||||
userData:
|
||||
assetBundleName:
|
||||
assetBundleVariant:
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,11 @@
|
||||
fileFormatVersion: 2
|
||||
guid: 3280a6148aa83ec3be2f6892fa4d8e2d
|
||||
MonoImporter:
|
||||
serializedVersion: 2
|
||||
defaultReferences: []
|
||||
executionOrder: 0
|
||||
icon: {instanceID: 0}
|
||||
externalObjects: {}
|
||||
userData:
|
||||
assetBundleName:
|
||||
assetBundleVariant:
|
||||
@@ -0,0 +1,446 @@
|
||||
using System;
|
||||
using System.Diagnostics;
|
||||
|
||||
namespace Unity.Burst.Intrinsics
|
||||
{
|
||||
public unsafe static partial class Arm
|
||||
{
|
||||
public unsafe partial class Neon
|
||||
{
|
||||
/// <summary>
|
||||
/// Evaluates to true at compile time if Armv8.1 Rounding Double Multiply Add/Subtract intrinsics are supported.
|
||||
/// </summary>
|
||||
public static bool IsNeonRDMASupported { get { return false; } }
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Vd.4H,Vn.4H,Vm.4H</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vqrdmlah_s16(v64 a0, v64 a1, v64 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Vd.2S,Vn.2S,Vm.2S</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vqrdmlah_s32(v64 a0, v64 a1, v64 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Vd.8H,Vn.8H,Vm.8H</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vqrdmlahq_s16(v128 a0, v128 a1, v128 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Vd.4S,Vn.4S,Vm.4S</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vqrdmlahq_s32(v128 a0, v128 a1, v128 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Vd.4H,Vn.4H,Vm.4H</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vqrdmlsh_s16(v64 a0, v64 a1, v64 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Vd.2S,Vn.2S,Vm.2S</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vqrdmlsh_s32(v64 a0, v64 a1, v64 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Vd.8H,Vn.8H,Vm.8H</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vqrdmlshq_s16(v128 a0, v128 a1, v128 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Vd.4S,Vn.4S,Vm.4S</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vqrdmlshq_s32(v128 a0, v128 a1, v128 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Vd.4H,Vn.4H,Vm.H[lane]</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vqrdmlah_lane_s16(v64 a0, v64 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Vd.8H,Vn.8H,Vm.H[lane]</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vqrdmlahq_lane_s16(v128 a0, v128 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Vd.4H,Vn.4H,Vm.H[lane]</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..7]</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vqrdmlah_laneq_s16(v64 a0, v64 a1, v128 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Vd.8H,Vn.8H,Vm.H[lane]</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..7]</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vqrdmlahq_laneq_s16(v128 a0, v128 a1, v128 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Vd.2S,Vn.2S,Vm.S[lane]</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..1]</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vqrdmlah_lane_s32(v64 a0, v64 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Vd.4S,Vn.4S,Vm.S[lane]</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..1]</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vqrdmlahq_lane_s32(v128 a0, v128 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Vd.2S,Vn.2S,Vm.S[lane]</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vqrdmlah_laneq_s32(v64 a0, v64 a1, v128 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Vd.4S,Vn.4S,Vm.S[lane]</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vqrdmlahq_laneq_s32(v128 a0, v128 a1, v128 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Vd.4H,Vn.4H,Vm.H[lane]</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vqrdmlsh_lane_s16(v64 a0, v64 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Vd.8H,Vn.8H,Vm.H[lane]</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vqrdmlshq_lane_s16(v128 a0, v128 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Vd.4H,Vn.4H,Vm.H[lane]</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..7]</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vqrdmlsh_laneq_s16(v64 a0, v64 a1, v128 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Vd.8H,Vn.8H,Vm.H[lane]</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..7]</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vqrdmlshq_laneq_s16(v128 a0, v128 a1, v128 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Vd.2S,Vn.2S,Vm.S[lane]</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..1]</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vqrdmlsh_lane_s32(v64 a0, v64 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Vd.4S,Vn.4S,Vm.S[lane]</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..1]</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vqrdmlshq_lane_s32(v128 a0, v128 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Vd.2S,Vn.2S,Vm.S[lane]</c></summary>
|
||||
/// <param name="a0">64-bit vector a0</param>
|
||||
/// <param name="a1">64-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>64-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v64 vqrdmlsh_laneq_s32(v64 a0, v64 a1, v128 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Vd.4S,Vn.4S,Vm.S[lane]</c></summary>
|
||||
/// <param name="a0">128-bit vector a0</param>
|
||||
/// <param name="a1">128-bit vector a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>128-bit vector</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static v128 vqrdmlshq_laneq_s32(v128 a0, v128 a1, v128 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Hd,Hn,Hm</c></summary>
|
||||
/// <param name="a0">Int16 a0</param>
|
||||
/// <param name="a1">Int16 a1</param>
|
||||
/// <param name="a2">Int16 a2</param>
|
||||
/// <returns>Int16</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static Int16 vqrdmlahh_s16(Int16 a0, Int16 a1, Int16 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Sd,Sn,Sm</c></summary>
|
||||
/// <param name="a0">Int32 a0</param>
|
||||
/// <param name="a1">Int32 a1</param>
|
||||
/// <param name="a2">Int32 a2</param>
|
||||
/// <returns>Int32</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static Int32 vqrdmlahs_s32(Int32 a0, Int32 a1, Int32 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Hd,Hn,Hm</c></summary>
|
||||
/// <param name="a0">Int16 a0</param>
|
||||
/// <param name="a1">Int16 a1</param>
|
||||
/// <param name="a2">Int16 a2</param>
|
||||
/// <returns>Int16</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static Int16 vqrdmlshh_s16(Int16 a0, Int16 a1, Int16 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Sd,Sn,Sm</c></summary>
|
||||
/// <param name="a0">Int32 a0</param>
|
||||
/// <param name="a1">Int32 a1</param>
|
||||
/// <param name="a2">Int32 a2</param>
|
||||
/// <returns>Int32</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static Int32 vqrdmlshs_s32(Int32 a0, Int32 a1, Int32 a2)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Hd,Hn,Vm.H[lane]</c></summary>
|
||||
/// <param name="a0">Int16 a0</param>
|
||||
/// <param name="a1">Int16 a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>Int16</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static Int16 vqrdmlahh_lane_s16(Int16 a0, Int16 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Hd,Hn,Vm.H[lane]</c></summary>
|
||||
/// <param name="a0">Int16 a0</param>
|
||||
/// <param name="a1">Int16 a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..7]</param>
|
||||
/// <returns>Int16</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static Int16 vqrdmlahh_laneq_s16(Int16 a0, Int16 a1, v128 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLAH Sd,Sn,Vm.S[lane]</c></summary>
|
||||
/// <param name="a0">Int32 a0</param>
|
||||
/// <param name="a1">Int32 a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..1]</param>
|
||||
/// <returns>Int32</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static Int32 vqrdmlahs_lane_s32(Int32 a0, Int32 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Hd,Hn,Vm.H[lane]</c></summary>
|
||||
/// <param name="a0">Int16 a0</param>
|
||||
/// <param name="a1">Int16 a1</param>
|
||||
/// <param name="a2">64-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>Int16</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static Int16 vqrdmlshh_lane_s16(Int16 a0, Int16 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Hd,Hn,Vm.H[lane]</c></summary>
|
||||
/// <param name="a0">Int16 a0</param>
|
||||
/// <param name="a1">Int16 a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..7]</param>
|
||||
/// <returns>Int16</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static Int16 vqrdmlshh_laneq_s16(Int16 a0, Int16 a1, v128 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
|
||||
/// <summary>Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
|
||||
/// <br/>Equivalent instruction: <c>SQRDMLSH Sd,Sn,Vm.S[lane]</c></summary>
|
||||
/// <param name="a0">Int32 a0</param>
|
||||
/// <param name="a1">Int32 a1</param>
|
||||
/// <param name="a2">128-bit vector a2</param>
|
||||
/// <param name="a3">Lane index to a2. Must be an immediate in the range of [0..3]</param>
|
||||
/// <returns>Int32</returns>
|
||||
[DebuggerStepThrough]
|
||||
public static Int32 vqrdmlshs_lane_s32(Int32 a0, Int32 a1, v64 a2, Int32 a3)
|
||||
{
|
||||
throw new NotImplementedException();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
fileFormatVersion: 2
|
||||
guid: 082593b719933f8b9f8feb40687d867e
|
||||
MonoImporter:
|
||||
serializedVersion: 2
|
||||
defaultReferences: []
|
||||
executionOrder: 0
|
||||
icon: {instanceID: 0}
|
||||
externalObjects: {}
|
||||
userData:
|
||||
assetBundleName:
|
||||
assetBundleVariant:
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,11 @@
|
||||
fileFormatVersion: 2
|
||||
guid: 05892f401645378395984f5ca02f11f1
|
||||
MonoImporter:
|
||||
serializedVersion: 2
|
||||
defaultReferences: []
|
||||
executionOrder: 0
|
||||
icon: {instanceID: 0}
|
||||
externalObjects: {}
|
||||
userData:
|
||||
assetBundleName:
|
||||
assetBundleVariant:
|
||||
Reference in New Issue
Block a user